STMicro to deploy humanoid robots to its legacy fabs in Europe — over 100 humanoid robots to be used for routine and physically demanding tasks in fight for efficiency

As cheap Chinese chips threaten to invade various sectors of the economy in Europe, STMicroelectronics is on track to improve the efficiency of its own fabs

IBM and Lam’s new partnership paves the way toward sub-1nm logic using High-NA EUV — Albany lab to pioneer dry resist process integration

Under the new agreement, the focus will shift to validating full process flows for nanosheet and nanostack device architectures and backside power delivery.

Meta reveals four new MTIA chips built for AI inference — to be released on a six-month cadence

All four chips have been developed in partnership with Broadcom and are scheduled for deployment within the next two years.

IBM and Lam Research team up on High NA EUV dry resist to push chip scaling past 1nm

The two companies have worked together for more than a decade, with IBM unveiling what it described as the world’s first 2nm node chip in 2021 as part of the partnership.

China’s top chip execs claim ASML alternative ‘small, fragmented, and weak’ — Chinese industry titans call for national effort to invest in advanced chipmaking tools

China’s most senior semiconductor executives issued a public call this week for a consolidated national effort to build a domestic alternative to Dutch lithography giant ASML.

ISSCC 2026: Rebellions details industry’s first quad-chiplet AI solution with UCIe interconnects — claims Rebel100 AI accelerator equals the power of Nvidia H200 with lower power envelope

Rebellions details how it developed one of the world’s first quad-chiplet AI accelerator with UCIe interconnects and how it did not use all of the technologies that the UCIe 1.0 specifications includes.

ISSCC 2026: AMD discloses how the Instinct MI355X doubled per-CU throughput despite lower compute unit count — ‘We are actually matching the performance of the more expensive and complex GB200’

Taking to the stage at ISSCC, AMD’s Ramasamy Adaikkalavan talked through how AMD managed to fit nearly double the compute throughput into the same die area as its predecessor,